The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device which comprises a power transistor, and a transistor constituting a control circuit, and is formed on an SOI (Silicon On Insulator) type bulk substrate.
It is difficult to form, as one chip, a power transistor and a transistor constituting a control circuit for driving the power transistor on the same major surface of a silicon substrate in view of dielectric isolation. A method of manufacturing a semiconductor device in which a power transistor and a transistor constituting a control circuit are formed as one chip using an SOI type bulk substrate is disclosed in Japanese Patent Laid-Open No. 1-144665.
FIGS. 5A to 5E show the conventional steps in manufacturing a semiconductor device. Referring to FIGS. 5A to 5E, in a method of manufacturing a semiconductor device described in the above document, an n.sup.+ -type epitaxial silicon layer 454b having a smooth surface is stacked on the major surface of an n.sup.- -type silicon base 454a to form a first silicon substrate 401. A silicon oxide film 402 is formed on the surfaces of the first silicon substrate 401 by thermal oxidation. The silicon oxide film 402 in a first region 452 on the major surface of the first silicon substrate 401 wherein a power transistor is to be formed, and the silicon oxide film 402 covering the remaining surfaces, except for the major surface, of the first silicon substrate 401 are removed. At this time, the silicon oxide film 402 in a second region 453, except for the first region 452, on the major surface of the first silicon substrate 401 remains (FIG. 5A).
Silicon is epitaxially grown to form an n +-type epitaxial silicon layer 432a in the first region 452 on the first silicon substrate 401 and an n.sup.+ -type polysilicon layer 432b in the second region 453 on the silicon oxide film 402. In this stage, since a stepped portion exists, the silicon layer is planished to eliminate this stepped portion and smooth the surface of the resultant structure. With this process, the n.sup.+ -type epitaxial silicon layer 432a and the n.sup.+ -type polysilicon layer 432b are respectively formed in the predetermined regions on the major surface of the first silicon substrate 401 (FIG. 5B). The planished major surface of an n.sup.+ -type second silicon substrate 403 is bonded to the major surface of the first silicon substrate 401, and the resultant structure is annealed at a temperature of 900.degree. C. or more, thereby obtaining a bulk substrate partially having an SOI structure (FIG. 5C). The other surface, opposite to the major surface, of the first silicon substrate 401 is planished to form an n.sup.- -type silicon layer 454aa consisting of the silicon base 454a and having a predetermined film thickness (FIG. 5D). Note that FIG. 5D shows that the top and bottom of FIG. 5C showing the first and second silicon substrates 401 and 403 are reversed.
The n.sup.- -type silicon layer 454aa and the n.sup.+ -type epitaxial silicon layer 454b are removed from predetermined portions in the second region 453 to form a groove 430 reaching the silicon oxide film 402. A silicon oxide film 433 is formed on the side surfaces of the groove 430, and a polysilicon film 434 is filled in the groove 430, thereby completing an element isolation region (FIG. 5E). A vertical n-channel power MOSFET is formed in the first region 452, and a control circuit comprising a p-channel MOSFET and the like is formed in the isolated second region 453.
The conventional method of manufacturing a semiconductor device described above has a problem in formation of a bulk substrate. That is, assume that the surface constituted by the n.sup.+ -type epitaxial silicon layer 432a and the n.sup.+ -type polysilicon layer 432b and having the stepped portion is polished to form the n.sup.+ -type epitaxial silicon layer 432a and the n.sup.+ -type polysilicon layer 432b on the same plane shown in FIG. 5B. Since the hardness of the n.sup.+ -type epitaxial silicon layer 432a is different from that of the n.sup.+ -type polysilicon layer 432b, it is difficult to make the surface constituted by the n.sup.+ -type epitaxial silicon layer 432a and the n.sup.+ -type polysilicon layer 432b a smooth mirror surface. Therefore, the manufacturing yield of a bulk substrate is low.
Furthermore, the conventional method of manufacturing a semiconductor device has problems that the step of forming the element isolation region in the second region 453 is complicated, and the manufacturing cost is high.